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Bit-Serial Architecture Optimizations - Raphael Weber
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
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Raphael Weber:

Bit-Serial Architecture Optimizations - neues Buch

2004, ISBN: 9783639328172

ID: 157149421

This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization. The latency of an evaluated IDCT implementation was reduced from 167 down to 67 clock cycles. The throughput of that implementation was improved by about 17%, while, as a side effect, area consumption was also reduced. Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture Buch (fremdspr.) Bücher>Fremdsprachige Bücher>Englische Bücher, [PU: VDM Verlag Dr. Müller, Saarbrücken]

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Bit-Serial Architecture Optimizations - Raphael Weber
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
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Raphael Weber:

Bit-Serial Architecture Optimizations - neues Buch

2004, ISBN: 9783639328172

ID: 157149421

This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization. The latency of an evaluated IDCT implementation was reduced from 167 down to 67 clock cycles. The throughput of that implementation was improved by about 17%, while, as a side effect, area consumption was also reduced. Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture Buch (fremdspr.) Bücher>Fremdsprachige Bücher>Englische Bücher, VDM Verlag

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Bit-Serial Architecture Optimizations - Raphael Weber
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Raphael Weber:
Bit-Serial Architecture Optimizations - neues Buch

2004

ISBN: 9783639328172

ID: 8e51d814aa29881629af9dc151ab40c1

Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization. The latency of an evaluated IDCT implementation was reduced from 167 down to 67 clock cycles. The throughput of that implementation was improved by about 17%, while, as a side effect, area consumption was also reduced. Bücher / Fremdsprachige Bücher / Englische Bücher 978-3-639-32817-2, VDM

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Bit-Serial Architecture Optimizations - Raphael Weber
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Raphael Weber:
Bit-Serial Architecture Optimizations - neues Buch

2004, ISBN: 9783639328172

ID: 143948396

This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization. The latency of an evaluated IDCT implementation was reduced from 167 down to 67 clock cycles. The throughput of that implementation was improved by about 17%, while, as a side effect, area consumption was also reduced. Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture Buch (fremdspr.) Bücher>Fremdsprachige Bücher>Englische Bücher, VDM

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Bit-Serial Architecture Optimizations - Weber, Raphael
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Weber, Raphael:
Bit-Serial Architecture Optimizations - Taschenbuch

2004, ISBN: 9783639328172

[ED: Softcover], [PU: VDM Verlag], This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization. The latency of an evaluated IDCT implementation was reduced from 167 down to 67 clock cycles. The throughput of that implementation was improved by about 17%, while, as a side effect, area consumption was also reduced.Versandfertig in 3-5 Tagen

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Details zum Buch
Bit-Serial Architecture Optimizations
Autor:

Raphael Weber

Titel:

Bit-Serial Architecture Optimizations

ISBN-Nummer:

3639328175

This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization. The latency of an evaluated IDCT implementation was reduced from 167 down to 67 clock cycles. The throughput of that implementation was improved by about 17%, while, as a side effect, area consumption was also reduced.

Detailangaben zum Buch - Bit-Serial Architecture Optimizations


EAN (ISBN-13): 9783639328172
ISBN (ISBN-10): 3639328175
Taschenbuch
Erscheinungsjahr: 2004
Herausgeber: VDM Verlag

Buch in der Datenbank seit 10.10.2014 07:57:44
Buch zuletzt gefunden am 07.11.2016 01:10:20
ISBN/EAN: 3639328175

ISBN - alternative Schreibweisen:
3-639-32817-5, 978-3-639-32817-2

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