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FPGA Implementation of MPEG-2 Video decoder - Jiwesh Kumar#Pranjal Pandey
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ISBN: 9783639295924

ID: 4c7ca5323a148f35bf19ba1a3b5a073f

FPGA Implementation of base layer MPEG-2 Video decoder The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 "university program" board. Bücher / Fremdsprachige Bücher / Englische Bücher 978-3-639-29592-4, VDM

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FPGA Implementation of MPEG-2 Video decoder - Jiwesh Kumar#Pranjal Pandey
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Jiwesh Kumar#Pranjal Pandey:

FPGA Implementation of MPEG-2 Video decoder - neues Buch

ISBN: 9783639295924

ID: 222857222

The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 ´´university program´´ board. FPGA Implementation of base layer MPEG-2 Video decoder Buch (fremdspr.) Bücher>Fremdsprachige Bücher>Englische Bücher, VDM

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FPGA Implementation of MPEG-2 Video decoder - Jiwesh Kumar
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Jiwesh Kumar:
FPGA Implementation of MPEG-2 Video decoder - neues Buch

ISBN: 9783639295924

ID: d2a1d78761607136af5f2067da9b9f77

The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 university program" board. Bücher / Naturwissenschaften, Medizin, Informatik & Technik / Technik / Maschinenbau, [PU: VDM Verlag Dr. Müller, Saarbrücken]

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FPGA Implementation of MPEG-2 Video decoder
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FPGA Implementation of MPEG-2 Video decoder - neues Buch

ISBN: 9783639295924

ID: d2a1d78761607136af5f2067da9b9f77

The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 university program" board. Bücher / Naturwissenschaften, Medizin, Informatik & Technik / Technik / Maschinenbau, [PU: VDM Verlag Dr. Müller, Saarbrücken]

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FPGA Implementation of MPEG-2 Video decoder - Jiwesh Kumar
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Jiwesh Kumar:
FPGA Implementation of MPEG-2 Video decoder - Taschenbuch

ISBN: 9783639295924

[ED: Taschenbuch], [PU: VDM Verlag], Neuware - The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 university program' board., [SC: 0.00], Neuware, gewerbliches Angebot, 220x150x6 mm, [GW: 125g]

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FPGA Implementation of MPEG-2 Video decoder
Autor:

Kumar, Jiwesh; Pandey, Pranjal

Titel:

FPGA Implementation of MPEG-2 Video decoder

ISBN-Nummer:

9783639295924

The MPEG-2 video bitstream without any Scalable Modes is called the Base layer bitstream. The work involves designing the MPEG-2 video decoder and related interfacing logic for reading the MPEG file from flash memory, storing the decoded data in SDRAM and displaying the video on the SVGA monitor by reading the data from SRAM. We have used the C code as the reference, provided by the MPEG Software Simulation Groups. The bit-by-bit algorithm, for decoding the base layer Mpeg-2 video stream, was abstracted from the C code and the corresponding hardware module for decoding the sequence was designed in VHDL using Quartus 6.2 tool supplied by Altera. The designed decoder module takes the serial bit stream in MPEG-2 format from Flash Memory as input, parses the system layer and decodes the video data. The output is provided in 24 bit RGB form. The MPEG-2 file resides in the flash memory, from where it is read byte-by-byte by the decoder module. The decoded frame is written to the SRAM, which dual ported to act as VIDEO RAM or VRAM. The VGA controller reads continuously from the VRAM and displays the video on monitor. The design was implemented on DE1 "university program" board.

Detailangaben zum Buch - FPGA Implementation of MPEG-2 Video decoder


EAN (ISBN-13): 9783639295924
ISBN (ISBN-10): 3639295927
Gebundene Ausgabe
Taschenbuch
Erscheinungsjahr: 2010
Herausgeber: VDM Verlag
72 Seiten
Gewicht: 0,125 kg
Sprache: eng/Englisch

Buch in der Datenbank seit 24.07.2007 06:16:18
Buch zuletzt gefunden am 08.11.2016 00:27:27
ISBN/EAN: 9783639295924

ISBN - alternative Schreibweisen:
3-639-29592-7, 978-3-639-29592-4

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