. .
Deutsch
Deutschland
Ähnliche Bücher
Weitere, andere Bücher, die diesem Buch sehr ähnlich sein könnten:
Buch verkaufen
Anbieter, die das Buch mit der ISBN 3639328175 ankaufen:
Suchtools
Anmelden

Anmelden mit Facebook:

Registrieren
Passwort vergessen?


Such-Historie
Merkliste
Links zu eurobuch.de

Dieses Buch teilen auf…
Buchtipps
Aktuelles
Tipp von eurobuch.de
Werbung
FILTER
- 0 Ergebnisse
Kleinster Preis: 42,99 €, größter Preis: 49,00 €, Mittelwert: 46,92 €
Bit-Serial Architecture Optimizations - Raphael Weber
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Raphael Weber:
Bit-Serial Architecture Optimizations - neues Buch

2004, ISBN: 9783639328172

ID: 157149421

This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization. The latency of an evaluated IDCT implementation was reduced from 167 down to 67 clock cycles. The throughput of that implementation was improved by about 17%, while, as a side effect, area consumption was also reduced. Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture Buch (fremdspr.) Bücher>Fremdsprachige Bücher>Englische Bücher, [PU: VDM Verlag Dr. Müller, Saarbrücken]

Neues Buch Thalia.de
No. 27537970 Versandkosten:, Versandfertig in 2 - 3 Tagen, DE (EUR 0.00)
Details...
(*) Derzeit vergriffen bedeutet, dass dieser Titel momentan auf keiner der angeschlossenen Plattform verfügbar ist.
Bit-Serial Architecture Optimizations - Raphael Weber
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Raphael Weber:
Bit-Serial Architecture Optimizations - neues Buch

2004, ISBN: 9783639328172

ID: 157149421

This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization. The latency of an evaluated IDCT implementation was reduced from 167 down to 67 clock cycles. The throughput of that implementation was improved by about 17%, while, as a side effect, area consumption was also reduced. Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture Buch (fremdspr.) Bücher>Fremdsprachige Bücher>Englische Bücher, VDM Verlag

Neues Buch Thalia.de
No. 27537970 Versandkosten:, Versandfertig in 2 - 3 Tagen, DE (EUR 0.00)
Details...
(*) Derzeit vergriffen bedeutet, dass dieser Titel momentan auf keiner der angeschlossenen Plattform verfügbar ist.
Bit-Serial Architecture Optimizations - Raphael Weber
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Raphael Weber:
Bit-Serial Architecture Optimizations - neues Buch

2004, ISBN: 9783639328172

ID: 8e51d814aa29881629af9dc151ab40c1

Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization. The latency of an evaluated IDCT implementation was reduced from 167 down to 67 clock cycles. The throughput of that implementation was improved by about 17%, while, as a side effect, area consumption was also reduced. Bücher / Fremdsprachige Bücher / Englische Bücher 978-3-639-32817-2, VDM

Neues Buch Buch.de
Nr. 27537970 Versandkosten:Bücher und alle Bestellungen die ein Buch enthalten sind versandkostenfrei, sonstige Bestellungen innerhalb Deutschland EUR 3,-, ab EUR 20,- kostenlos, Bürobedarf EUR 4,50, kostenlos ab EUR 45,-, Versandfertig in 5 - 7 Tagen, zzgl. Versandkosten
Details...
(*) Derzeit vergriffen bedeutet, dass dieser Titel momentan auf keiner der angeschlossenen Plattform verfügbar ist.
Bit-Serial Architecture Optimizations - Raphael Weber
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Raphael Weber:
Bit-Serial Architecture Optimizations - neues Buch

2004, ISBN: 9783639328172

ID: 143948396

This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization. The latency of an evaluated IDCT implementation was reduced from 167 down to 67 clock cycles. The throughput of that implementation was improved by about 17%, while, as a side effect, area consumption was also reduced. Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture Buch (fremdspr.) Bücher>Fremdsprachige Bücher>Englische Bücher, VDM

Neues Buch Thalia.at
No. 27537970 Versandkosten:, Versandfertig in 4 - 6 Tagen, AT (EUR 0.00)
Details...
(*) Derzeit vergriffen bedeutet, dass dieser Titel momentan auf keiner der angeschlossenen Plattform verfügbar ist.
Weber, Raphael: Bit-Serial Architecture Optimizations
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Weber, Raphael: Bit-Serial Architecture Optimizations - neues Buch

ISBN: 9783639328172

ID: 175830500

Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture Latency and Throughput Optimization, based on Synchronizers and Routers for a Bit-Serial Fully Pipelined Architecture Bücher > English, International > Gebundene Ausgaben, [PU: VDM Verlag Dr. Müller, Saarbrücken]

Neues Buch eBook.de
No. 14519906 Versandkosten:zzgl. Versandkosten
Details...
(*) Derzeit vergriffen bedeutet, dass dieser Titel momentan auf keiner der angeschlossenen Plattform verfügbar ist.

Details zum Buch
Bit-Serial Architecture Optimizations
Autor:

Raphael Weber

Titel:

Bit-Serial Architecture Optimizations

ISBN-Nummer:

This work presents latency optimizations for a specific hardware architecture, which was developed based on the combination of different design paradigms and thus requires sophisticated design optimizations. The architecture comprises synchronous and systematic bit-serial processing without a central controlling instance. It was patented in 2004 and targets future high-speed applications due to the abdication of long wires. So-called routers, achieving a reconfigurable system, can overcome the application specificity of the basic version of the architecture. This work focuses on the challenge of latency optimizations also covering data synchronization problems when implementing the architecture. We propose and evaluate several variations for the realization. The latency of an evaluated IDCT implementation was reduced from 167 down to 67 clock cycles. The throughput of that implementation was improved by about 17%, while, as a side effect, area consumption was also reduced.

Detailangaben zum Buch - Bit-Serial Architecture Optimizations


EAN (ISBN-13): 9783639328172
ISBN (ISBN-10): 3639328175
Taschenbuch
Erscheinungsjahr: 2004
Herausgeber: VDM Verlag

Buch in der Datenbank seit 10.10.2014 07:57:44
Buch zuletzt gefunden am 13.03.2017 21:39:12
ISBN/EAN: 3639328175

ISBN - alternative Schreibweisen:
3-639-32817-5, 978-3-639-32817-2


< zum Archiv...
Benachbarte Bücher