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Verification and Validation in Systems Engineering
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2010, ISBN: 9783642152276

Erscheinungsdatum: 18.11.2010, Medium: Buch, Einband: Gebunden, Titel: Verification and Validation in Systems Engineering, Titelzusatz: Assessing UML/SysML Design Models, Auflage: 2010, A… Mehr…

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Verification and Validation in Systems Engineering Assessing UML/SysML Design Models - Alawneh, Luay; Debbabi, Mourad; Hassaïne, Fawzi; Jarraya, Yosr; Soeanu, Andrei
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Alawneh, Luay; Debbabi, Mourad; Hassaïne, Fawzi; Jarraya, Yosr; Soeanu, Andrei:

Verification and Validation in Systems Engineering Assessing UML/SysML Design Models - gebunden oder broschiert

2010, ISBN: 3642152279

2010 Gebundene Ausgabe EDV / Theorie / Software-Entw. / Software Engineering, Wartung und Reparaturen, IT, Betriebssysteme, Software Engineering, Systemanalyse und -design, Model Checki… Mehr…

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Mourad Debbabi:
Verification and Validation in Systems Engineering: Assessing UML/SysML Design Models - gebrauchtes Buch

2010

ISBN: 9783642152276

2010-02-02. New. Ships with Tracking Number! INTERNATIONAL WORLDWIDE Shipping available. May be re-issue. Buy with confidence, excellent customer service!, 2010-02-02

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Debbabi, Mourad; Hassaïne, Fawzi; Jarraya, Yosr; Soeanu, Andrei; Alawneh, Luay:
Verification and Validation in Systems Engineering: Assessing UML/SysML Design Models - gebunden oder broschiert

2010, ISBN: 9783642152276

Springer, 2010-11-19. Hardcover. Like New., Springer, 2010-11-19

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Mourad Debbabi, Fawzi Hassaïne, Yosr Jarraya, Andrei Soeanu, Luay Alawneh:
Verification and Validation in Systems Engineering: Assessing UML/SysML Design Models - gebunden oder broschiert

2010, ISBN: 9783642152276

Springer, 2010-11-19. 2010. Hardcover. Used:Good., Springer, 2010-11-19

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Verification and Validation in Systems Engineering

Verification and validation represents an important process used for the quality assessment of engineered systems and their compliance with the requirements established at the beginning of or during the development cycle.Debbabi and his coauthors investigate methodologies and techniques that can be employed for the automatic verification and validation of systems engineering design models expressed in standardized modeling languages. Their presentation includes a bird's eye view of the most prominent modeling languages for software and systems engineering, namely the Unified Modeling Language (UML) and the more recent Systems Modeling Language (SysML). Moreover, it elaborates on a number of quantitative and qualitative techniques that synergistically combine automatic verification techniques, program analysis, and software engineering quantitative methods applicable to design models described in these modeling languages. Each of these techniques is additionally explained using a case study highlighting the process, its results, and resulting changes in the system design.Researchers in academia and industry as well as students specializing in software and systems engineering will find here an overview of state-of-the-art validation and verification techniques. Due to their close association with the UML standard, the presented approaches are also applicable to industrial software development.

Detailangaben zum Buch - Verification and Validation in Systems Engineering


EAN (ISBN-13): 9783642152276
ISBN (ISBN-10): 3642152279
Gebundene Ausgabe
Erscheinungsjahr: 2010
Herausgeber: Springer Berlin
248 Seiten
Gewicht: 0,545 kg
Sprache: eng/Englisch

Buch in der Datenbank seit 2009-11-06T05:49:03+01:00 (Berlin)
Detailseite zuletzt geändert am 2020-12-15T11:31:43+01:00 (Berlin)
ISBN/EAN: 9783642152276

ISBN - alternative Schreibweisen:
3-642-15227-9, 978-3-642-15227-6


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