2010, ISBN: 3838381874

[EAN: 9783838381879], Livro novo, [SC: 55.0], [PU: LAP LAMBERT Academic Publishing Sep 2010], This item is printed on demand - Print on Demand Titel. Neuware -Full-chip verication require… Mehr…

[EAN: 9783838381879], Livro novo, [SC: 55.0], [PU: LAP LAMBERT Academic Publishing Sep 2010], This item is printed on demand - Print on Demand Titel. Neuware -Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verication of the grid. We propose a power grid verication technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. We propose one technique where we verify the worst case voltage as an optimization problem. Using this voltage verication and the constraints we also check the worst case delay of critical paths within the design. Lastly we implement a method of partitioning that allows us to verify grids of an industrial size within reasonable simulation times.Books on Demand GmbH, Überseering 33, 22297 Hamburg 104 pp. Englisch, Books<

2010, ISBN: 9783838381879

Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally… Mehr…

Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verication of the grid. We propose a power grid verication technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. We propose one technique where we verify the worst case voltage as an optimization problem. Using this voltage verication and the constraints we also check the worst case delay of critical paths within the design. Lastly we implement a method of partitioning that allows us to verify grids of an industrial size within reasonable simulation times. Worst case analysis with power constraints and optimization theory Bücher > Fremdsprachige Bücher > Englische Bücher Taschenbuch 01.09.2010 Buch (fremdspr.), LAP Lambert Academic Publishing, .201<

2010, ISBN: 3838381874

[EAN: 9783838381879], Livro novo, [SC: 16.0], [PU: LAP LAMBERT Academic Publishing Sep 2010], This item is printed on demand - it takes 3-4 days longer - Neuware -Full-chip verication req… Mehr…

[EAN: 9783838381879], Livro novo, [SC: 16.0], [PU: LAP LAMBERT Academic Publishing Sep 2010], This item is printed on demand - it takes 3-4 days longer - Neuware -Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verication of the grid. We propose a power grid verication technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. We propose one technique where we verify the worst case voltage as an optimization problem. Using this voltage verication and the constraints we also check the worst case delay of critical paths within the design. Lastly we implement a method of partitioning that allows us to verify grids of an industrial size within reasonable simulation times. 104 pp. Englisch, Books<

2010, ISBN: 9783838381879

Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally… Mehr…

Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verication of the grid. We propose a power grid verication technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. We propose one technique where we verify the worst case voltage as an optimization problem. Using this voltage verication and the constraints we also check the worst case delay of critical paths within the design. Lastly we implement a method of partitioning that allows us to verify grids of an industrial size within reasonable simulation times. Worst case analysis with power constraints and optimization theory Buch (fremdspr.) Taschenbuch 01.09.2010 Bücher>Fremdsprachige Bücher>Englische Bücher, LAP Lambert Academic Publishing, .201<

2010, ISBN: 9783838381879

gewerbliches Angebot, [SC: 0.00], Neuware, [PU: LAP LAMBERT Academic Publishing], 104, [GW: 173g], [ED: Taschenbuch], DE, Full-chip verication requires one to check if the power grid volt… Mehr…

gewerbliches Angebot, [SC: 0.00], Neuware, [PU: LAP LAMBERT Academic Publishing], 104, [GW: 173g], [ED: Taschenbuch], DE, Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verication of the grid. We propose a power grid verication technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. We propose one technique where we verify the worst case voltage as an optimization problem. Using this voltage verication and the constraints we also check the worst case delay of critical..., Banküberweisung, PayPal, [CT: Sonstiges / Sonstiges]<