ISBN: 9783838381879

Denis Kouroussis,Paperback, English-language edition,Pub by AV Akademikerverlag GmbH & Co. KG. Textbooks New Books ~~ Technology~~ Electrical Power-Grid-Verification~~Denis-Kouroussis AV Akademikerverlag GmbH & Co. KG. Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verication of the grid. We propose a power grid verication technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. We propose one technique where we verify the worst case voltage as an optimization problem. Using this voltage verication and the constraints we also check the worst case delay of critical paths within the design. Lastly we implement a method of partitioning that allows us to verify grids of an industrial size within reasonable simulation times.

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2010, ISBN: 9783838381879

Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verication of the grid. We propose a power grid verication technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. We propose one technique where we verify the worst case voltage as an optimization problem. Using this voltage verication and the constraints we also check the worst case delay of critical paths within the design. Lastly we implement a method of partitioning that allows us to verify grids of an industrial size within reasonable simulation times. Worst case analysis with power constraints and optimization theory Bücher > Fremdsprachige Bücher > Englische Bücher Taschenbuch 01.09.2010 Buch (fremdspr.), LAP Lambert Academic Publishing, .201

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2010, ISBN: 9783838381879

Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verication of the grid. We propose a power grid verication technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. We propose one technique where we verify the worst case voltage as an optimization problem. Using this voltage verication and the constraints we also check the worst case delay of critical paths within the design. Lastly we implement a method of partitioning that allows us to verify grids of an industrial size within reasonable simulation times. Worst case analysis with power constraints and optimization theory Buch (fremdspr.) Taschenbuch 01.09.2010 Bücher>Fremdsprachige Bücher>Englische Bücher, LAP Lambert Academic Publishing, .201

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ISBN: 9783838381879

Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verication of the grid. We propose a power grid verication technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. We propose one technique where we verify the worst case voltage as an optimization problem. Using this voltage verication and the constraints we also check the worst case delay of critical paths within the design. Lastly we implement a method of partitioning that allows us to verify grids of an industrial size within reasonable simulation times. Worst case analysis with power constraints and optimization theory Buch (fremdspr.) Bücher>Fremdsprachige Bücher>Englische Bücher, LAP Lambert Academic Publishing

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2010, ISBN: 9783838381879

Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally expensive, because of the large variety of possible circuit behaviors that would need to be simulated; it also has the disadvantage that it requires full knowledge of the details of the circuit attached to the grid, thereby precluding early verication of the grid. We propose a power grid verication technique that can be applied before the complete circuit has been designed and without exact knowledge of the circuit currents. We use current constraints, which are upper bound constraints on the currents that can be drawn from the grid, as a way to capture the uncertainty about the circuit details and activity. We propose one technique where we verify the worst case voltage as an optimization problem. Using this voltage verication and the constraints we also check the worst case delay of critical paths within the design. Lastly we implement a method of partitioning that allows us to verify grids of an industrial size within reasonable simulation times. Buch (fremdspr.) Taschenbuch, LAP LAMBERT Academic Publishing, 01.09.2010, LAP LAMBERT Academic Publishing, 2010

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ISBN: 9783838381879

Denis Kouroussis,Paperback, English-language edition,Pub by AV Akademikerverlag GmbH & Co. KG. Textbooks New Books ~~ Technology~~ Electrical Power-Grid-Verification~~Denis-Kouroussis AV … Mehr…

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2010, ISBN: 9783838381879

Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally… Mehr…

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2010

## ISBN: 9783838381879

Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally… Mehr…

No. 23974568. Versandkosten:Zzgl. Versandkosten. (EUR 15.52)

ISBN: 9783838381879

Full-chip verication requires one to check if the power grid voltage drop does not exceed a certain threshold. The traditional simulation-based solution to this problem is computationally… Mehr…

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2010, ISBN: 9783838381879

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** Detailangaben zum Buch - Power Grid Verification**

EAN (ISBN-13): 9783838381879

ISBN (ISBN-10): 3838381874

Gebundene Ausgabe

Taschenbuch

Erscheinungsjahr: 2010

Herausgeber: LAP Lambert Acad. Publ.

104 Seiten

Gewicht: 0,174 kg

Sprache: eng/Englisch

Buch in der Datenbank seit 2009-08-28T19:10:53+02:00 (Berlin)

Detailseite zuletzt geändert am 2019-11-15T14:45:51+01:00 (Berlin)

ISBN/EAN: 9783838381879

ISBN - alternative Schreibweisen:

3-8383-8187-4, 978-3-8383-8187-9

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